1. Field of the Invention
This invention relates to the making of electronic components such as semiconductor wafer VLSI and ULSI interconnects, and, more particularly, to a copper electroplating bath and method to plate the vias and trenches and other small features of the components to provide void-free fill for features below about 0.2 microns and with high aspect ratios.
2. Description of Related Art
The demand for manufacturing semiconductor integrated circuit (IC) devices such as computer chips with high circuit speed, high packing density and low power dissipation requires the downward scaling of feature sizes in ultra-large-scale integration (ULSI) and very-large-scale integration (VLSI) structures. The trend to smaller chip sizes and increased circuit density requires the miniaturization of interconnect features which severely penalizes the overall performance of the structure because of increasing interconnect resistance and reliability concerns such as fabrication of the interconnects and electromigration.
In general, such structures use silicon wafers with silicon dioxide (SiO2) being the dielectric material and openings are formed in the SiO2 dielectric layer in the shape of vias and trenches which are then metallized forming the interconnects. Increased miniaturization is reducing the openings to submicron sizes (e.g., 0.2 micron and lower) and increasing the aspect ratio (ratio of the height of the opening to the width of the opening) of the features.
Copper is becoming the metal of choice to form the interconnects and copper can be deposited on substrates by plating (such as electroless and electrolytic), sputtering, plasma vapor deposition (PVD) and chemical vapor deposition (CVD). It is generally recognized that a plating-based deposition is the best method to apply copper to the device since it can provide high deposition rates and low tool costs. However, plating methods must meet the stringent requirements of the semiconductor industry. For example, the copper deposits must be uniform and capable of filling the extremely small trenches and vias of the device. The deposition of copper from acid copper baths is recognized in the electronics industry as the leading candidate to copper plate integrated circuit devices. It will be appreciated by those skilled in the art however that other metal baths such as Ni, Au, Ag, Zn, Pd, Sn, etc. may be used with the additive system of the present invention to provide improved metal plating baths and that this description is directed to copper for convenience.
Copper electroplating, in general, involves deposition of a copper layer onto a surface by means of electrolysis using a consumable copper electrode or an insoluble anode. In the consumable electrolytic plating process, the copper electrode is consumed during the plating operation and must be replaced periodically during the plating operation. When plating using insoluble anodes, these anodes are not consumed in the plating process and do not have to be replaced.
A preferred plating apparatus and method is described in U.S. Pat. No. 6,024,856 assigned to the same assignee as the present application.
It has been found that conventional copper electroplating baths are only marginally effective when the plating surface contains very small features (i.e., submicron) and/or with high aspect ratios. In particular, the copper fill in a small feature tends to have voids and these voids may increase the resistance or even cause an open circuit of the conductive path intended to be formed by the copper deposited in the feature. This problem becomes critical in using copper electrodeposition processes in integrated circuit fabrication because contact and via holes in an integrated circuit can be 0.2 micron or less in width, with an aspect ratio of up to four-to-one or greater and voids in the contacts and vias may easily result causing high resistance interconnects or even open-circuits.
As the copper interconnect technologies have advanced to more complex geometries, so have the demands for better copper electroplating baths to fill the vias and trenches on wafers that are getting smaller in feature size and higher in aspect ratios. Consequently, the conventional acid copper electrochemical deposition systems can no longer meet the higher performance level needed to fill void-free feature sizes below about 0.20 micron. The prior art has attempted to improve the acid copper bath chemistry but there is still a need for improved acid copper baths for the plating of high performance semiconductor wafers and other such electronic components.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a copper electroplating bath which provides void-free fill features particularly below about 0.20 microns, when plating electronic components such as semiconductor wafers having trenches and vias and other small features.
It is another object of the present invention to provide a method for copper electroplating electronic components such as semiconductor wafers particularly those having features below about 0.20 microns.
A further object of the invention is to provide semiconductor wafers plated using the method and copper electroplating bath of the invention.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
In accordance with the above goals and objectives, in the present invention there is provided in one embodiment an improved copper electroplating bath for use in electroplating electronic components such as semiconductor wafers having submicron vias and trenches particularly those having features below about 0.20 microns. Broadly stated, in an aqueous acidic electrolyte containing copper in an amount sufficient to electrodeposit copper on a substrate, the improvement comprises incorporating in the electrolyte an additive system comprising:
a bath soluble organic divalent sulfur compound corresponding to the formula:
xe2x80x83R1xe2x80x94(S)nxe2x80x94RXO3Mxe2x80x83xe2x80x83(I)
wherein:
M is hydrogen, alkali metal or ammonium as needed to satisfy the valence;
X is S or P;
R is an alkylene or cyclic alkylene group of 1 to 8 carbon atoms, an aromatic hydrocarbon or an aliphatic aromatic hydrocarbon of 6 to 12 carbon atoms;
n is 1 to 6, preferably 1 to 2; and
R1 is MO3XR wherein M, X and R are as defined above or by the formula: 
wherein:
R2 and R3 are hydrogen, an alkyl group of 1 to 4 carbon atoms, a heterocyclic group or an aromatic group; and
a bath soluble polyether compound selected from the group consisting of block copolymers of polyoxyethylene and polyoxypropylene, a polyoxyethylene or polyoxypropylene derivative of a polyhydric alcohol and a mixed polyoxyethylene and polyoxypropylene derivative of a polyhydric alcohol.
The bath soluble polyether compound is in one embodiment a block copolymer of polyoxyethylene and polyoxypropylene glycols. More preferably, the bath soluble polyether compound is a polyoxyethylene or polyoxypropylene derivative of glycerine or other polyhydric alcohol such as sorbitol, mannitol and pentaerythritol and the like and most preferably is a mixed polyoxyethylene and polyoxypropylene derivative of a polyhydric alcohol, particularly glycerine.
In another embodiment a method is provided for plating copper onto electronic components such as semiconductor wafers having submicron vias and trenches using the copper plating bath of the invention.
In a further embodiment semiconductor wafers and other electronic components having sub-micron features made using the copper electroplating bath and method of the invention are also provided.